The present invention generally relates to semiconductor devices and more particularly to a semiconductor package that has a single in-line package structure.
In order to improve the efficiency of mounting of semiconductor devices on a support substrate such as a printed circuit board, a package structure designed for surface mounting is used extensively. By using the surface mounting technology, the semiconductor device can be mounted on the circuit board without providing holes for inserting leads of the device. The soldering of the leads is achieved by merely placing the device on the circuit board and passing the device and the circuit board through a heating furnace for causing a reflow of soldering alloy. Thereby, the efficiency of the mounting process is improved significantly and the fabrication cost of electronic apparatuses that use the semiconductor devices is significantly reduced.
In order to mount the semiconductor devices as many as possible on a single support substrate, a so-called single in-line package (SIP) is proposed. In the single in-line package, the leads are provided along a single edge of a flat package body to extend perpendicularly with respect to the edge, thereof and the package body is held upright on the substrate by inserting the leads into the corresponding holes of the substrate. As the package body is held vertically on the substrate, one can increase the number of the packages that are mounted on the single substrate. Further, such a structure is advantageous for cooling the device.
In order to combine the advantageous feature of the single in-line package with the advantageous feature of the surface mounting technology, a package structure shown in FIG. 1 is proposed in the U.S. Pat. No. 4,975,763.
Referring to FIG. 1, the package designated by a numeral 1 includes a flat resin package body 2 that accommodates therein a semiconductor chip 3. At an edge 2a of the flat package body 2, there are provided a number of leads each having an inner lead part 4a connected to a bonding pad of the chip 3 and an outer lead part 4b extending outward from the edge 2a. Further, the outer lead part 4b of the leads 4 is bent laterally with respect to the extending direction of the leads 4. In order to support the package body 2 on the substrate at the time of mounting, there is provided a pair of studs 5a each including a stop portion 6 and a cylindrical clip portion 7 of a reduced diameter for inserting into a corresponding hole provided on the substrate.
FIG. 2 shows the mounting of the package 1 on a substrate 8, wherein the substrate 8 is formed with a hole 8a for holding the clip portion 7 of the stud 5. There, the portion 7 is inserted into the hole 8a as shown in FIG. 2 and the package body 2 is held upright on the substrate 8. The substrate 8 carries thereon a conductor pattern 8b for wiring, and the lead 4 is contacted with the conductor pattern 8b when the package 1 is held on the substrate 8. By passing the substrate 8 together with the package 1 in the state shown in FIG. 2, through a furnance the soldering alloy provided on the conductor pattern 8b causes a reflow and the lead 4 is soldered firmly upon the conductor pattern 8.
In this conventional package structure, there is a problem in that one has to provide the hole 8a on the substrate 8 in correspondence to the stud 5 for holding the package body 2 on the substrate 8, As each lead 4 has to engage with corresponding pattern 8b when the package is mounted, it is necessary that the hole 8a be formed with high precision. This requirement is particularly acute in the recent semiconductor devices that have a large number of leads on the package body. The high precision required by this formation of the hole and the insertion of the stud into the hole undermine the advantageous feature of the surface mounting technology, and the efficiency of mounting is inevitably deteriorated.
The package of FIG.1 has another drawback in that each lead 4 has to extend straight from the package body 2 at least for a distance corresponding to the length of the stop portion 6. This straight part of the lead 4 contributes to nothing but causes an unwanted delay of the electrical signals that is carried therethrough. With the increasing operational speed of the semiconductor devices, such a delay may cause a serious problem in the exchange of electric signals between the chip and the conductor pattern on the substrate. Further, such a structure having a long, exposed lead is vulnerable to external noises. As long as one uses the stud for supporting the package body on the substrate, one cannot reduce the length of the lead satisfactorily.
In order to eliminate the problem pertinent to the conventional package of FIG. 1, another single in-line package structure is proposed in the U.S. patent application Ser. No. 881,899 filed May 12, 1992.
FIG. 3 shows the bottom view of the package proposed in the foregoing U.S. '899 application.
Referring to FIG. 3, the single in-line type package includes a semiconductor chip not shown in the illustration and a package body 11 that accommodates the semiconductor chip therein. The package body 11 is defined by a pair of opposing major surfaces 11a and 11b and surrounded by a side wall 11d, 11e connecting the two opposing major surfaces 11a and 11b, wherein the side wall includes a substantially straight bottom edge part 11f that extends substantially straight, when viewed in the direction perpendicular to the major surfaces 11a and 1lb. A plurality of leads 14 are held by the package body 11 to extend substantially perpendicularly to the edge surface.
Each of the leads 14 is connected to the semiconductor chip electrically, wherein each lead consists of an inner lead part located inside the package body and an outer lead part 14a located outside the package body. There, outer lead part 14a is bent laterally at a boundary between the inner part and the outer part. The leads are bent in one of a first and a second direction such that they are opposite from their adjacent leads and substantially perpendicular to the opposing major surfaces. In addition, the package of FIG. 3 includes a plurality of support legs 12a, 12b, 13a and 13b held by the package body 11 to extend substantially perpendicularly to the edge surface 11f, wherein each of the support legs consists of an inner part located inside the package body and an outer part located outside the package body. There, the outer part of the support leg such as the leg 12a is bent laterally in one of the first and second directions at a boundary between the inner part and the outer part such that the package body is held upright when placed on a substrate.
According to the foregoing construction of FIG.3, the package body 11 is held upright on the substrate by the support legs by simply placing the package body 11 on a substrate such as a printed circuit board. By causing a reflow of a solder alloy in this state, each interconnection lead is connected electrically to a corresponding conductor pattern on the substrate. In other words, the semiconductor package can be mounted on the substrate by the surface mounting technology. Thereby, one can eliminate the process for inserting a stud into a corresponding hole of the substrate as practiced in the conventional device shown in FIG. 1. Associated therewith, one can eliminate the process for forming the holes accurately in the substrate. Thereby, the efficiency of mounting the package on the substrate is significantly improved. The package structure of FIG.3 has another advantageous feature in that the interconnection lead 14 is bent laterally at the root part where it emerges from the package body 11. Thereby, the unnecessary extension of the leads is eliminated and the delay of the electric signals hitherto caused by such a straight part of the lead at the outside of the package body is eliminated. Without the lead extensions the semiconductor device is less vulnerable to external noises. Obviously, this advantageous feature is obtained as a result of use of the support legs 12a, 12b, 13a and 13b that are also bent at the root part.
In spite of various advantageous features described above, the package of FIG.3 still has a drawback in that laterally extending support legs tend to cause an interference with adjacent packages when the packages are mounted with a reduced mutual separation. Thus, one has to secure a relatively large distance between adjacent package bodies when a number of packages are mounted on a common substrate. Unfortunately, such a situation occurs relatively frequently when mounting memory devices on a mother board of computers. Further, because of the limited allowable lateral length of the support legs, the package of FIG.3 has a substantial risk that the package body may fall due to blowing of a hot air for causing the reflow of the solder alloy.